This invention pertains to semiconductive processing methods of forming integrated circuitry, as well as to semiconductive device circuitry.
A common method of forming memory devices is to form an array of devices (a so-called memory array), and to form control devices at a periphery of the array. The memory array can comprise, for example, a dynamic random access memory (DRAM) array comprising arrays of capacitors and transistors. The peripheral circuitry can comprise, for example, transistors. Frequently, the memory array circuitry and the peripheral circuitry will be covered by insulative materials. Conductive contact plugs can be formed to extend through the insulative materials to electrically connect peripheral circuitry and memory array circuitry to one another, or to other circuitry.
A continuing goal in semiconductor device fabrication is to minimize process steps. Accordingly, it would be desired to develop processing methods which reduce processing steps associated with forming memory array circuitry and peripheral circuitry.
In one aspect, the invention encompasses a method of forming circuitry. A capacitor electrode is formed over one region of a substrate and a conductive diffusion barrier layer is formed proximate the electrode. A dielectric layer is formed. The diffusion barrier layer is between the electrode and the dielectric layer. A conductive plug is formed over another region of the substrate. The conductive plug comprises a same material as the conductive diffusion barrier layer and at least a portion of the conductive plug is formed simultaneously with the conductive diffusion barrier layer.
In another aspect, the invention encompasses an integrated circuit comprising a capacitor and a conductive plug wherein the conductive plug and capacitor include a common and continuous layer.
In yet another aspect, the invention encompasses a circuit construction. The circuit construction includes a substrate having a memory array region and a region that is peripheral to the memory array region. The circuit construction also includes a capacitor construction over the memory array region of the substrate. The capacitor construction comprises a storage node, a dielectric layer and a cell plate layer. The dielectric layer is between the storage node and the cell plate layer. The circuit construction further includes an electrical interconnect over the peripheral region. The interconnect is electrically connected to the cell plate layer and extends between the cell plate layer and the substrate.